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LH5164A/AH
FEATURES * 8,192 x 8 bit organization * Access times: 80/100 ns (MAX.) * Low-power consumption: Operating: 303 mW (MAX.) LH5164A/D/N @ 80 ns 248 mW (MAX.) LH5164A/D/N/T @ 100 ns 275 mW (MAX.) LH5164AH/HD/HN/HT @ 100 ns Standby: LH5164A/D/N/T: 5.5 W (MAX.) LH5164AH/HD/HN/HT: TA 85C: 16.5 W (MAX.) TA 70C: 5.5 W (MAX.) * Fully-static operation * Three-state outputs * Single +5 V power supply * TTL compatible I/O * Wide temperature range available LH5164A: -10 to +70C LH5164AH: -40 to +85C * Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP 28-pin, 8 x 13 mm2 TSOP (Type I) DESCRIPTION
The LH5164A/AH are static RAMs organized as 8,192 x 8 bits. It is fabricated using silicon-gate CMOS process technology. The LH5164AH is designed for wide temperature range from -40 to +85C.
CMOS 64K (8K x 8) Static RAM
PIN CONNECTIONS
28-PIN DIP 28-PIN SK-DIP 28-PIN SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
5164A-1
TOP VIEW
Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages
28-PIN TSOP (Type I)
TOP VIEW
OE A11 A9 A8 CE2 WE VCC NC A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2
5164A-8
Figure 2. Pin Connections for TSOP Package
1
LH5164A/AH
CMOS 64K (8K x 8) Static RAM
A3 A4
7
ROW DECODERS ROW ADDRESS BUFFERS
6 A5 5 A6 4 A7 3 A8 25 A9 24 A12 2
MEMORY ARRAY (256 x 256)
28 VCC 14 GND
I/O1 11 I/O2 12 I/O3 13 I/O4 15 I/O5 16 I/O6 17 I/O7 18 I/O8 19
I/O CIRCUITS DATA CONTROL COLUMN DECODERS
COLUMN ADDRESS BUFFER
WE 27
OE 22 CE2 26 CE1 20 10 A0 NOTE: Pin numbers apply to 28-pin DIP, SK-DIP, or SOP. 9 A1 8 A2 21 A10 23 A11
5164A-2
Figure 3. LH5164A/AH Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A12 CE1 - CE2 WE OE
Address inputs Chip Enable input Write Enable input Output Enable input
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
TRUTH TABLE
CE1 CE2 WE OE MODE I/O 1 - I/O 8 SUPPLY CURRENT NOTE
H X L L L
NOTE: 1. X = H or L
X L H H H
X X L H H
X X X L H
Deselect Deselect Write Read Output disable
High-Z High-Z DIN DOUT High-Z
Standby (ISB) Standby (ISB) Operating (ICC) Operating (ICC) Operating (ICC)
1 1 1
2
CMOS 64K (8K x 8) Static RAM
LH5164A/AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL 80 ns RATING 100 ns RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to VCC + 0.3 -10 to +70 -55 to +150
-0.3 to +7.0 -0.3 to VCC + 0.3 -10 to +70 -40 to +85 -55 to +150
V V C C C
1 1, 2 3 4
NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width 50 ns. 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT
RECOMMENDED OPERATING CONDITIONS 1
PARAMETER SYMBOL MIN. 80 ns TYP. MAX. MIN. 100 ns TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC VIH VIL
4.5 2.2 -0.3
5.0
5.5 VCC + 0.3 0.8
4.5 2.2 -0.3
5.0
5.5 VCC + 0.3 0.8
V V V 2
NOTES: 1. TA = -10 to +70C (LH5164A/AD/AN/AT), TA = -40 to +85C (LH5164AH/AHD/AHN/AHT). 2. VIN (MIN.) = -3.0 V for pulse width 50 ns.
DC CHARACTERISTICS 1 (VCC = 5 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input leakage current Output leakage current
ILI ILO
VIN = 0 to VCC CE1 = VIH or CE2 = VIL or OE = V IH or WE = VIL VI/O = 0 to VCC CE1 = VIL, VIN = VIL or VIH tCYCLE = 80 ns CE2 = VIH, Outputs open CE1 = VIL, VIN = VIL or VIH CE2 = VIH, Outputs open tCYCLE = 100 ns
-1.0 -1.0
1.0 1.0 55 45 50
A A mA 2 3 mA
Operating current
ICC
Standby current
ISB1 VOL VOH
Output voltage
CE1 = VIL, VIN = 0.2 V or tCYCLE = VCC - 0.2 V 1.0 s CE2 = VIH, Outputs open CE1 = VIH or CE2 = VIL TA 70C CE2 0.2 V or CE1 VCC - 0.2 V TA 85C IOL = 2.1 mA IOH = -1 mA
10 5 1.0 3.0 0.4 2.4 mA A A V V
2, 3, 4 3, 4
NOTES: 1. TA = -10 to 70C (LH5164A/AD/AN/AT), TA = -40 to +85C (LH5164AH/AHD/AHN/AHT) 2. LH5164A/AD/AN/AT 3. LH5164AH/AHD/AHN/AHT 4. CE2 should be VCC - 0.2 V or 0.2 V when CE1 VCC - 0.2 V
3
LH5164A/AH
CMOS 64K (8K x 8) Static RAM
AC CHARACTERISTICS 1 (1) READ CYCLE (VCC = 5 V 10%)
PARAMETER SYMBOL MIN. 80 ns MAX. MIN. 100 ns MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time (CE1) (CE2)
tRC tAA tACE1 tACE2 tOE tOH (CE1) (CE2) tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
80 80 80 80 40 10 10 10 5 0 0 0 30 30 20
100 100 100 100 40 10 10 10 5 0 0 0 30 30 20
ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1
Output enable access time Output hold time Chip enable to output in Low-Z
Output enable to output in Low-Z Chip enable to output in High-Z (CE1) (CE2)
Output disable to output in High-Z
(2) WRITE CYCLE (VCC = 5 V 10%)
PARAMETER SYMBOL MIN. 80 ns MAX. MIN. 100 ns MAX. UNIT NOTE
Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Output active from end of write WE to output in High-Z OE to output in High-Z
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ
80 70 70 0 60 0 40 0 10 0 0
30 20
100 80 80 0 60 0 40 0 10 0 0
30 20
ns ns ns ns ns ns ns ns ns ns ns
2 2 2
NOTES: 1. TA = -10 to +70C (LH5164A/AD/AN/AT), TA = -40 to +85C (LH5164AH/AHD/AHN/AHT) 2. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude Input rise/fall time Timing reference level Output load conditions
0.6 to 2.4 V 10 ns 1.5 V 1TTL + CL (100 pF)
1
NOTE: 1. Includes scope and jig capacitance.
4
CMOS 64K (8K x 8) Static RAM
LH5164A/AH
CAPACITANCE 1 (TA = 25C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance Input/output capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: 1. This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS 1
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Data retention voltage
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3 V, CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 40C TA = 25C TA = 70C
2.0
5.5 0.2 0.4 0.6
V A A A A A A ns ns
2 2, 3 2, 3 2, 3 2, 4 2, 4 2, 4 5
Data retention current
ICCDR VCCDR = 3 V, CE2 0.2 V or CE1 VCCDR - 0.2 V
0.2 0.6 1.5
Chip disable to data retention Recovery time
tCDR tR
0 tRC
NOTES: 1. TA = -10 to +70C (LH5164A/AD/AN/AT), TA = -40 to +85C (LH5164AH/AHD/AHN/AHT) 2. CE2 should be VCCDR - 0.2 V or 0.2 V when CE1 VCCDR - 0.2 V 3. LH5164A/AD/AN/AT 4. LH5164AH/AHD/AHN/AHT 5. t RC = Read cycle time
5
LH5164A/AH
CMOS 64K (8K x 8) Static RAM
CE1 CONTROL (NOTE) VCC 4.5 V tCDR
DATA RETENTION MODE tR
2.2 V VCCDR CE1 0V CE1 VCCDR - 0.2 V
CE2 CONTROL DATA RETENTION MODE VCC 4.5 V CE2 tCDR tR
VCCDR 0.8 V 0V CE2 0.2 V NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode.
5164A-6
Figure 4. Low Voltage Data Retention
tRC
A0 - A12 tAA tACE1 CE1 tLZ1 tACE2 CE2 tLZ2 tOE tOLZ OE tOHZ I/O1 - I/O8 NOTE: WE = 'HIGH.'
5164A-3
tHZ1
tHZ2
DATA VALID
tOH
Figure 5. Read Cycle
6
CMOS 64K (8K x 8) Static RAM
LH5164A/AH
tWC
A0 - A12
OE
tAW tCW (NOTE 2)
(NOTE 4) tWR
CE1 tCW tWR
CE2 tAS (NOTE 3) WE tOHZ (NOTE 5) DOUT HIGH-Z tDW DIN (NOTE 6)
DATA VALID
tWP (NOTE 1)
tWR
tDH
NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 6. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164A-4
Figure 6. Write Cycle 1
7
LH5164A/AH
CMOS 64K (8K x 8) Static RAM
tWC
A0 - A12 tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4)
CE2 tAS (NOTE 3) WE (NOTE 5) DOUT tWZ HIGH-Z tDW DIN (NOTE 7)
DATA VALID
tWP (NOTE 1)
tWR
tOW (NOTE 6) tDH
OE = 'LOW' NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the outputs will remain high-impedance. 7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
5164A-5
Figure 7. Write Cycle 2
8
CMOS 64K (8K x 8) Static RAM
LH5164A/AH
PACKAGE DIAGRAMS
28DIP (DIP028-P-0600)
28 15
DETAIL
13.45 [0.530] 12.95 [0.510]
1 36.30 [1.429] 35.70 [1.406]
14
0 TO 15 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP.
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN.
DIMENSIONS IN MM [INCHES]
28DIP-2
28-pin, 600-mil DIP
28DIP (DIP028-P-0300)
28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.02] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP.
DETAIL
0 TO 15
DIMENSIONS IN MM [INCHES]
28DIP-6
28-pin, 300-mil SK-DIP
9
LH5164A/AH
CMOS 64K (8K x 8) Static RAM
28SOP (SOP028-P-0450)
1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457]
0.50 [0.020] 0.30 [0.012]
28
10.60 [0.417]
1 18.20 [0.717] 17.80 [0.701]
14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28SOP
28-pin, 450-mil SOP
10
CMOS 64K (8K x 8) Static RAM
LH5164A/AH
28TSOP (TSOP028-P-0813)
0.28 [0.011] 0.12 [0.005] 28 0.55 [0.022] TYP. 15
12.00 [0.472] 11.60 [0.457]
13.70 [0.539] 13.10 [0.516]
12.60 [0.496] 12.20 [0.480]
1 8.20 [0.323] 7.80 [0.307]
14 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] 0.425 [0.017] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.00 [0.000]
28TSOP
DETAIL
0 - 10
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28-pin, 8 x 13 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5164A X X Device Type Operating Package Temperature - ## Speed L Power Low-power standby 10 100 Access Time (ns) 80 80 Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil SK-DIP (SK-DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) T 28-pin, 8 x 13 mm2 TSOP (Type I) (TSOP028-P-0813) Blank -10 to 70C H -40 to +85C CMOS 64K (8K x 8) Static RAM Example: LH5164AD-10L (CMOS 64K (8K x 8) Static RAM, 100 ns, Low-power standby, 28-pin, 300-mil SK-DIP) 5164A-7
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